50 pts Draw the schematic Diagram for the following VHDL by hand, show the Registers/D-Flip Flops (the DFF's will be active high reset, active high enable, and rising edge clock) and all combinational logic (AND/OR etc) gates, also you may need a multiplexer. Denote inputs and outputs of the top level sigsmall box with an X through it: 1) library ieee: 2Be ieee.atd_logic 1164.all; entity de1_soc_top is port( clk in std logic ina in atd_logic inb in ad logic inc in std_logic: uta:out std logic: outh :out std log1c outc out stdlogic) Pan 14 nd del_soc top; 15 16 larchitecture rtl or de1_soc_top is 18 eignal pipe it onee :etd logic: 1 aignal pipe_it_twice :atd logici 20 signal pipc_it_threc std logic; 21 signal sigahb std logic