5.10 In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2. P1 P2 L1 Size 2 KiB 4 KiB L1 Miss Rate 80% 60% L1 Hit Time 0.66ns 0.90ns 5.10.1 [5] Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? cycles)? 5.10.2 [10] Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2? Which processor is faster? (When we say a "base CPI of 1.0", we mean that instructions complete in one cycle, unless either the instruction access or the data access causes a cache miss.) For the next three problems, we will consider the addition of an L2 cache to P1 (to presumably make up for its limited L1 cache capacity). Use the Ll cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate. L2 Size L2 Miss Rate L2 Hit Time 1 MiB 95% 5.62ns 5.10.4 | 10] Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache? 5.10.6 [10] What would the L2 miss rate need to be in order for P1 with an L2 cache to be faster than P1 without an L2 cache? 5.10.7 [15] What would the L2 miss rate need to be in order for P1 with an L2 cache to be faster than P2 without an L2 cache