5.12 Multilevel caching is an important technique to overcome the limited amount of space that a first-level cache can provide while still maintaining its speed. Consider a processor with the following parameters 3 3.5% 1.5 2GHz 100ns First Level Cache miss rate is per instruction. Assume the total number of L1 cache misses 7% | 12 cycles 28 cycles 1.5% (instruction and data combined) is equal to 7% of the number of instructions. 5.12.1 [10] Calculate the CPI for the processor in the table using: 1) only a first-level cache, 2) a second-level direct-mapped cache, and 3) a second-level eight-way set associative cache. How do these numbers change if main memory access time doubles? (Give each change as both an absolute CPI and a percent change.) Notice the extent to which an L2 cache can hide the effects of a slow memorv. 5.12 Multilevel caching is an important technique to overcome the limited amount of space that a first-level cache can provide while still maintaining its speed. Consider a processor with the following parameters 3 3.5% 1.5 2GHz 100ns First Level Cache miss rate is per instruction. Assume the total number of L1 cache misses 7% | 12 cycles 28 cycles 1.5% (instruction and data combined) is equal to 7% of the number of instructions. 5.12.1 [10] Calculate the CPI for the processor in the table using: 1) only a first-level cache, 2) a second-level direct-mapped cache, and 3) a second-level eight-way set associative cache. How do these numbers change if main memory access time doubles? (Give each change as both an absolute CPI and a percent change.) Notice the extent to which an L2 cache can hide the effects of a slow memorv