5.1.a Fill in truth table for the following latch made from cross coupled NAND gates. A BQ(t) y(t) Q(t+delta) y(t+delta) 5.1.b what would be a good label for the inputs A and B in terms of their effect on Q and y (assume y is usually Q)? What state of inputs A and B should be avoided (analogous to the inputs to the standard NOR based SR latch that should be avoided 5.1.c Draw a state diagram for this NAND based latch using the signal names A and B as the inputs and Q and y as the outputs. We've started the diagram for you with 2 of the 4 states The states are labelled Qy so 01 means Q-0 and y-1. 01 10 5.1.d Convert the latch from 5.1.a into a clocked latch using the minimum number of 2-input NAND gates and one inverter (hint: look at the D latch we designed in class using NOR gates and AND gates and one inverter). Draw a schematic of your D-latch using the cross coupled NAND gates (show the cross coupled NAND gates in your schematic). Label the data input D and the clock input C. 5.1.a Fill in truth table for the following latch made from cross coupled NAND gates. A BQ(t) y(t) Q(t+delta) y(t+delta) 5.1.b what would be a good label for the inputs A and B in terms of their effect on Q and y (assume y is usually Q)? What state of inputs A and B should be avoided (analogous to the inputs to the standard NOR based SR latch that should be avoided 5.1.c Draw a state diagram for this NAND based latch using the signal names A and B as the inputs and Q and y as the outputs. We've started the diagram for you with 2 of the 4 states The states are labelled Qy so 01 means Q-0 and y-1. 01 10 5.1.d Convert the latch from 5.1.a into a clocked latch using the minimum number of 2-input NAND gates and one inverter (hint: look at the D latch we designed in class using NOR gates and AND gates and one inverter). Draw a schematic of your D-latch using the cross coupled NAND gates (show the cross coupled NAND gates in your schematic). Label the data input D and the clock input C