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6 . 1 9 In future systems, we expect to see heterogeneous computing platforms constructed out of heterogeneous CPUs. We have begun to see some
In future systems, we expect to see heterogeneous computing platforms
constructed out of heterogeneous CPUs. We have begun to see some appear in the
embedded processing market in systems that contain both floatingpoint DSPs and
microcontroller CPUs in a multichip module package.
Assume that you have three classes of CPU:
CPU AA moderatespeed multicore CPU with a floatingpoint unit that can
execute multiple instructions per cycle.
CPU BA fast singlecore integer CPU ie no floatingpoint unit that can
execute a single instruction per cycle.
CPU CA slow vector CPU with floatingpoint capability that can execute
multiple copies of the same instruction per cycle.
Assume that our processors run at the following frequencies:
CPU A can execute two instructions per cycle, CPU B can execute one
instruction per cycle, and CPU C can execute eight instructions through the
same instruction per cycle. Assume all operations can complete execution in a
single cycle of latency without any hazards.
All three CPUs have the ability to perform integer arithmetic, though CPU B
cannot perform floating point arithmetic. CPU A and B have an instruction set
similar to a LEGv processor. CPU C can only perform floating point add and
subtract operations, as well as memory loads and stores. Assume all CPUs have
access to shared memory and that synchronization has zero cost.
The task at hand is to compare two matrices and that each contain
floatingpoint elements. The output should be a count of the number of indices
where the value in was larger or equal to the value in
$ Describe how you would partition the problem on the three
different CPUs to obtain the best performance.
$ What kind of instruction would you add to the vector CPU
to obtain better performance?
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