6. a. Draw a top level diagram of major components in a computer equipment h. What are interruptstrat Pgr fle af contrl wtout and with interrupts. Additionally show transfer of control with multiple interrupts. . Discuss Bus intercorrection scterne. Crimpare and contrast between traditional bus architecture and high perfarrne bus architerture. What ar thr basic elernents f bus d d. Share bus architecture was the standard approach to interconnection between the processors and other components for many years. However conternporary designs require port-to paint approach rather th?n shared bus. Discuss these approaches (with appropriate illustration) and why they offer extensively improved perforri ne e. Consider a hypiathetical iropirccessor generating a 1G-bit address (rexanple, assurie that the prograrn counter and the address registers are 16 bits wideand havng a 1t-bit data bus. I. What is the maximum memory address space that the processor can access directly If it is connected to a 16- it menory? ii. What is the axirnum mernnry address space that the ressrcan acress cdirectly if it is connected to an -bit memory"? iii. what architectural feitures will allow this rn?crcprocessor to acces5 a separate 1 0 space"? iv.If an input and ari output instructin cari specify an8-bit I/ port nuer, how rnay 8-bit O ports ca? the microprocessor support? How many 16-bit I/0 ports? Explain f. Consider?32-bit rnicroprocessor, with a 16-bit extern! dita bus, driven by an 8-MHz input clock. Assume that this miressras a bus ryle whase ninirnum duratio eqsr input cleock ryclrs. What is thr maximum data transfer rate across the bus that this microprocessor can sustain, in bytess?To increase its perfrane, wuld it be better tonake its external data bus 32 bits ar ta deoable the exterrl clk frequenry supplied to the nitroprocessor? State ay other assuripitions you rnakr, nd exp. Hint:Determine the number of bytes that can be transferred perbus cycle 6. a. Draw a top level diagram of major components in a computer equipment h. What are interruptstrat Pgr fle af contrl wtout and with interrupts. Additionally show transfer of control with multiple interrupts. . Discuss Bus intercorrection scterne. Crimpare and contrast between traditional bus architecture and high perfarrne bus architerture. What ar thr basic elernents f bus d d. Share bus architecture was the standard approach to interconnection between the processors and other components for many years. However conternporary designs require port-to paint approach rather th?n shared bus. Discuss these approaches (with appropriate illustration) and why they offer extensively improved perforri ne e. Consider a hypiathetical iropirccessor generating a 1G-bit address (rexanple, assurie that the prograrn counter and the address registers are 16 bits wideand havng a 1t-bit data bus. I. What is the maximum memory address space that the processor can access directly If it is connected to a 16- it menory? ii. What is the axirnum mernnry address space that the ressrcan acress cdirectly if it is connected to an -bit memory"? iii. what architectural feitures will allow this rn?crcprocessor to acces5 a separate 1 0 space"? iv.If an input and ari output instructin cari specify an8-bit I/ port nuer, how rnay 8-bit O ports ca? the microprocessor support? How many 16-bit I/0 ports? Explain f. Consider?32-bit rnicroprocessor, with a 16-bit extern! dita bus, driven by an 8-MHz input clock. Assume that this miressras a bus ryle whase ninirnum duratio eqsr input cleock ryclrs. What is thr maximum data transfer rate across the bus that this microprocessor can sustain, in bytess?To increase its perfrane, wuld it be better tonake its external data bus 32 bits ar ta deoable the exterrl clk frequenry supplied to the nitroprocessor? State ay other assuripitions you rnakr, nd exp. Hint:Determine the number of bytes that can be transferred perbus cycle