6. Caches Consider a three level memory hierarchy consisting of an L1 cache backed by an L2 cache backed by memory.

a. For each address in the sequence of addresses below, mark whether it is a hit (H) or a miss (M). Use a dash (-) to indicate no access (I.e. if a hit in the L1, L2 has no access). For each hit or miss, indicate the set in which it occurred.

b. What is the miss rate for L1 and L2?

c. Let L1 access time be 5 cycles, L2 be 25 cycles, and Memory be 500 cycles. What is the expected access time for the entire hierarchy given the sequence in a.

L1 2 Sets Bytes/Block Ways 8 16 64 00 00 01 01 01 01 00 00 01 01 01 00 00 00 01 01 11 00 00 00 10 10 10 10 01 00 10 10 10 10 00 00 10 10 10 10 00 00 01 01 01 00