[6 points] Complete the truth table given the combinatorial logic circuit below. Use 0 to represent OV (FALSE) and 1 to represent 3.3V (TRUE) and put the inputs in binary counting order from 000 to 111 binary. 13) If the minimum gate delay is 2 ns and the maximum gate delay is 10 ns. How long would you have to wait after the inputs change to insure all utputs are valid? How long could you wait to sample the original output value after the inputs change? ns