6. Using Verilog HDL, design a binary full adder using three NOT-MAJORITY gates and two inverters as shown below. Write a test bench and use Modelsim to verify the functionality of your design. MAJ OO MAJ Cout a b Cin MAJ Sum 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1