7. [50] You are to design an 8 GB memory subsystem for a desktop PC system employing DDR3 SDRAM chips on a standard DIMM with ECc and 72 data lines (for data and ECC). The SDRAM chips use a 1KB page size, 8 banks. The DIMMs employed are 4GB PC3-19200 with timing (10-12-12-31).Assume a cache line fill results in 64 bytes being read from the DIMM. a) b) c) d) [5] How many SDRAMs are on the DIMM if 512M x8 SDRAMs are used? [5] How many ranks would there be per DIMM? [5] How many ranks are there in the memory system? [5] What would be the impact of using 256M x 16 SDRAMs on the memory organization? re there any disadvantages? e) [5] What is the maximum bandwidth of one DIMM? f [5] How much time lin ns) is required from the presentation of the activate command until the end of the cycle during which the last bytes of data are transferred? Assume the bank is precharged. g we could always arrang e it so that the bytes we want from memory are among the first 8 bytes of the burst, how much faster on average can we expect to get the data? Assume that the memory controller implements a closed-page policy, pre-charging after each access to a bank. Give your answer as a percentage improvement over not using this technique. h) [5] What is the ratio of the amount of time it will take to complete a read from a location requiring a bank activate command (page empty) versus a read from a location in an already open page (page hit)? i5) Assume a scenario in which the memory controller implements an open page policy. If a long sequence of memory references results in all page misses, what bandwidth can we expect? bank utlization device utilization data bus CAS%) column read precharge i[5] How does the result in (i) above compare with the maximum theoretical maximum bandwidth of the PC3-19200 DIMM 7. [50] You are to design an 8 GB memory subsystem for a desktop PC system employing DDR3 SDRAM chips on a standard DIMM with ECc and 72 data lines (for data and ECC). The SDRAM chips use a 1KB page size, 8 banks. The DIMMs employed are 4GB PC3-19200 with timing (10-12-12-31).Assume a cache line fill results in 64 bytes being read from the DIMM. a) b) c) d) [5] How many SDRAMs are on the DIMM if 512M x8 SDRAMs are used? [5] How many ranks would there be per DIMM? [5] How many ranks are there in the memory system? [5] What would be the impact of using 256M x 16 SDRAMs on the memory organization? re there any disadvantages? e) [5] What is the maximum bandwidth of one DIMM? f [5] How much time lin ns) is required from the presentation of the activate command until the end of the cycle during which the last bytes of data are transferred? Assume the bank is precharged. g we could always arrang e it so that the bytes we want from memory are among the first 8 bytes of the burst, how much faster on average can we expect to get the data? Assume that the memory controller implements a closed-page policy, pre-charging after each access to a bank. Give your answer as a percentage improvement over not using this technique. h) [5] What is the ratio of the amount of time it will take to complete a read from a location requiring a bank activate command (page empty) versus a read from a location in an already open page (page hit)? i5) Assume a scenario in which the memory controller implements an open page policy. If a long sequence of memory references results in all page misses, what bandwidth can we expect? bank utlization device utilization data bus CAS%) column read precharge i[5] How does the result in (i) above compare with the maximum theoretical maximum bandwidth of the PC3-19200 DIMM
