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7. (6 points) Fill in the timing diagram below assuming the AND gate has a delay of 1 and the OR gates have a delay

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7. (6 points) Fill in the timing diagram below assuming the AND gate has a delay of 1 and the OR gates have a delay of 2. Assume that all wire delays are 0 and a negated input does not add to the delay of a gate. (Hint: fill in the waveforms for the intermediate gate outputs.)

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