7. Assume that the memory address of a computer system can address up to 4G bytes, and so the address is 32-bit wide. Suppose we use a one-level 256K-byte cache to improve the performance. The cache is organized in a way that each block consists of 32 bytes. (a) [6%] Suppose the cache is direct mapped. Which bit fields of the address indicate the tag, the cache index, and the offset, respectively? (b) [6%) Suppose the cache is fully associative. Which bit fields of the address indicate the tag and the offset, respectively? (c) [6%] Suppose the cache is 4-way set associative. Which bit fields of the address indicate the tag, the cache index, and the offset, respectively