7.4 MASTER-SLAVE AND EDGE-TRIGGERED D FLIP-FLOPS 397 Preset Clock- Clear (a) Circuit Preset Clear ClockQ Clear (b) Graphical symbol (c) Adding a synchronous clear 7. Figure 7.14 (c), p. 397 shows how to implement a positive-edge-triggered D flip-flop with a synchronous clear. Design a logic circuit so that the D flip-flop has both a synchronous clear and preset. Design the logic circuit such that when !Clear !Preset the flip-flop is neither cleared nor preset. (12.5/9 points)