8. (10) The following figure shows a tree structured carry-save adder that is designed to add 8 4-bit binary numbers (A+B+C+D+E+F+G+H). (a) Complete that connections between the upper and lower blocks by labeling the inputs on the lower block using the signal names from the outputs of the upper blocks. (b) Assuming each full or half-adder is implemented with two level logic and needs 2T delay, what is the propagation delay of the whole adder? (c) Place an "H in the cells that could be implemented with half-adders. How many full-adders are required? How many half-adders are required? (d) Assume that we implemented this same adder using traditional ripple carry adders in a tree structured manner ((A+B) + (C+D)) + ((E+F) + (G+H))). How many full-adders would be required? How many half-adders would be required? f3 g3 h3 f2 g2 h2 fl gl h1 fo go ho b3 c3 d3 b2 c2 d2 blcl di b0c0 do e3 e2 el e0 a3 a2 al a0 y4 z4 y3 z3 y2 22 yl zl yo w4 x4 w3 x3 w2x2 wl xl wo r6 r5 r4 r3 r2 r1 ro 8. (10) The following figure shows a tree structured carry-save adder that is designed to add 8 4-bit binary numbers (A+B+C+D+E+F+G+H). (a) Complete that connections between the upper and lower blocks by labeling the inputs on the lower block using the signal names from the outputs of the upper blocks. (b) Assuming each full or half-adder is implemented with two level logic and needs 2T delay, what is the propagation delay of the whole adder? (c) Place an "H in the cells that could be implemented with half-adders. How many full-adders are required? How many half-adders are required? (d) Assume that we implemented this same adder using traditional ripple carry adders in a tree structured manner ((A+B) + (C+D)) + ((E+F) + (G+H))). How many full-adders would be required? How many half-adders would be required? f3 g3 h3 f2 g2 h2 fl gl h1 fo go ho b3 c3 d3 b2 c2 d2 blcl di b0c0 do e3 e2 el e0 a3 a2 al a0 y4 z4 y3 z3 y2 22 yl zl yo w4 x4 w3 x3 w2x2 wl xl wo r6 r5 r4 r3 r2 r1 ro