8. (5 points) This question refers to the pipelined datapath with forwarding in Figure 4.56 of the textbook and also given in the course notes Consider the instructions 200 addi $1, $0, 4 204 add $3, $4, $1 208 add $3, $1, $3 Consider the situation when the 100 addi instruction is in the WB stage, the 104 add instruction is in the MEM stage, and the 108 add instruction is in the EX stage. In the figure below, trace back each of the two inputs to the ALU through the MUXes back to the appropriate set of pipeline registers.e., trace a path from the ALU back to the pipeline registers where the values are stored). You may use bold dark or zigzag lines to clearly indicate your work. add $3,$1,$3 add $3,$4,SI addi $1,$0.4 ID/EX WB EX/MEM MEMAWB IF/ID EX WB Registers ALU Instruction memory Data memory F/ID.RegisterRs IF/ID.RegisterRt IF/1D RegisterRt IF/ID.RegisterRd Rt EXMEM.RegisterRd MI Forwarding unit MEM/WB.RegisterRd 8. (5 points) This question refers to the pipelined datapath with forwarding in Figure 4.56 of the textbook and also given in the course notes Consider the instructions 200 addi $1, $0, 4 204 add $3, $4, $1 208 add $3, $1, $3 Consider the situation when the 100 addi instruction is in the WB stage, the 104 add instruction is in the MEM stage, and the 108 add instruction is in the EX stage. In the figure below, trace back each of the two inputs to the ALU through the MUXes back to the appropriate set of pipeline registers.e., trace a path from the ALU back to the pipeline registers where the values are stored). You may use bold dark or zigzag lines to clearly indicate your work. add $3,$1,$3 add $3,$4,SI addi $1,$0.4 ID/EX WB EX/MEM MEMAWB IF/ID EX WB Registers ALU Instruction memory Data memory F/ID.RegisterRs IF/ID.RegisterRt IF/1D RegisterRt IF/ID.RegisterRd Rt EXMEM.RegisterRd MI Forwarding unit MEM/WB.RegisterRd