8.6 [M] A computer with a 16-bit word length has a direct-mapped cache, used for both instruc- tions and data. Memory addresses are 16 bits long, and the memory is byte-addressable. The cache is small for illustrative purposes. It contains only four 16-bit words. Each word constitutes a cache block and has an associated 13-bit tag, as shown in Figure P8.2a. Words are accessed in the cache using the low-order 3 bits of an address. When a miss occurs during a Read operation for either an instruction or a data operand, the requested word is read from the main memory and sent to the processor. At the same time, it is copied into the cache, and its block number is stored in the associated tag. Consider the following short loop, in which all instructions are 16 bits long: LOOP: Add R0, (R1)+ Decrement R2 BNE LOOP Assume that, before this loop is entered, registers R0, R1, and R2 contain 0, 054E, and 3, respectively. Also assume that the main memory contains the data shown in Figure P8.2b, where all entries are given in hexadecimal notation. The loop starts at location LOOP = 02EC. The Autoincrement address mode in the Add instruction is used to access successive numbers in a 3-number list and add them into register R0. The counter register, R2, is decremented until it reaches 0, at which point an exit is made from the loop. (a) Starting with an empty cache, show the contents of the cache, including the tags, at the end of each pass through the loop. (b) Assume that the access times of the cache and the main memory are and 10 , respec- tively. Calculate the execution time for each pass, counting only memory access times.

13 bits 16 bits 054E Tag A03C Data 05D9 10D7 (a) Cache (b) Main memory Figure P8.2 Cache and main memory contents in Problem 8.6 13 bits 16 bits 054E Tag A03C Data 05D9 10D7 (a) Cache (b) Main memory Figure P8.2 Cache and main memory contents in Problem 8.6