8.8a help

of 8.6 (a) Assume the inverters have a delay of 1 ns and the other gates have a delay of 2 ns Initially AB-C. 0 and D = 1; C changes tol at time 2 ns. Draw a timing dia- gram showing the glitch corresponding to the hazard. (b) Modit'y the cireuit so that it is hazard free. (Leave the cireuit as a two-level. OR AND circuit,) 8.7 A two-level, NOR-NOR circuit implements the function (a) Find all hazards in the circuil. (b) Redesign the circuit as a two-level, NOR-NOR circuil free of all hazards and using a minimum number of gates. 8.8 RA. B, C.D) -m0:2.3.5.6.7.8.9.13.15) (a) Find three different minimum AND OR circuils that implement F. Identily two hazards in each circuit. Then lind an AND OR circuit for i that has no hazards (b) There are two minimum OR AND circuits for F: cach has one hazard Identily the hazarnd in cach circuit, and then find an OR-AND circuit for F that has no hazards Combinational Circuit Design and Simulation Using Gates 245