9. Suppose we have a 5-stage MIPS pipeline with these latencies: 300 ps IF ID EX MEM 400 ps WB a) What is the cycle time of this pipeline? What is the clock rate in GHz? b) Suppose we can split any stage of the pipeline into two stages, with equal latencies Which stage would you choose? What would be the cycle time of the new pipeline? 250 ps 300 ps 350 ps