9.14

Consider a combinational circuit that requires 128 ns to process input data and assume that it can always be divided into smaller parts of equal propagation delays. Let T_cq and T_setup of the register be 1 and 3 ns respectively. Determine the throughput and delay (a) of the original circuit. (b) if the circuit is converted into a 2-stage pipeline. (c) if the circuit is converted into a 4-stage pipeline. (d) if the circuit is converted into an 8-stage pipeline. (e) if the circuit is converted into a 16-stage pipeline. (f) if the circuit is converted into a 32-stage pipeline. Convert the reduced-xor circuit in Section 7.4.1 into a four-stage pipelined circuit