A 1 to 8 demultiplexer with d Din, address inputs So, S, S, as the LSB) and y, to , as demultiplexed outputs, is to be using two 2 to 4 decoders (with and address inputs A, and A) in the figure Din, So, S, and S . connected to P, Q, R and S necessarily in this order. The input connections to P, Q, terminals should be A 1 to 8 demultiplexer with d Din, address inputs So, S, S, as the LSB) and y, to , as demultiplexed outputs, is to be using two 2 to 4 decoders (with and address inputs A, and A) in the figure Din, So, S, and S . connected to P, Q, R and S necessarily in this order. The input connections to P, Q, terminals should be