A 1 to 8 demultiplexer with da Din, address inputs Sy, S,, S, ( as the LSB) and , to Y, as t demultiplexed outputs, is to be using two 2 to 4 decoders (with e and address inputs A, and 4 ) a in the figure Din So, S, and S, connected to P, Q, R and S necessarily in this order. The re input connections to P, Q, R IS terminals should be A 1 to 8 demultiplexer with da Din, address inputs Sy, S,, S, ( as the LSB) and , to Y, as t demultiplexed outputs, is to be using two 2 to 4 decoders (with e and address inputs A, and 4 ) a in the figure Din So, S, and S, connected to P, Q, R and S necessarily in this order. The re input connections to P, Q, R IS terminals should be