A 3-bit logical shift right of 10100110 results in * 00010100 O 11010100 11100011 10101010 Multiple streams could be a solution to: * Data hazards None of the answers O Control hazards Loop buffer This type of instruction does not need a write back stage: * Load Store None of the answers O Substract This is the picture of: * Instruction R Memory Operand Registers Immediate addressing technique Register addressing technique None of the answers Direct addressing technique Assume a simplified five-stage pipeline (FI, DI, FO, El and wo), in which each stage takes one clock cycle. Assume we want to execute the following program: X = X +8 then Y= Y + 8 Where X and Y are registers, the whole program using pipeline paradigm will be fully accomplished in * 8 clock cycles None of the answers 6 clock cycles 5 clock cycles 07 clock cycles