(a) (4 points) What is the purpose of the following components in an SRAM array: (i) row decoder, (ii) wordlines, (iii) bitlines, (iv) column multiplexer?

(b) (2 points) Why do DRAMs typically use multiplexed address lines, whereas SRAMs do not?

(c) (3 points) What is the minimum burst length supported in DDR2? Why do DDRx memories not support a burst length of 1?

(d) (3 points) If the DRAM row (page) size is decreased, what impact does it have on the following: (i) power, (ii) row buffer hit rate?