A 4-bit ripple-carry adder (RCA4) with 4-bit inputs A and B respectively, and 4bit output sum and 1-bit output carryout cout is implemented using 1 halfadder (HA) and 3 full adders (FA). Additional constraints are as follows: - The (propagation) delay of AND/OR/NOT gate is 1 microsecond. AND and OR gates are constrained to be 2-inputs only. Ignore any delays due to parasitic resistance of the wires. - FA and HA are implemented using AND/OR/NOT gates ONLY. NOTE: Write numeric value only (i.e., if the answer is 4 microseconds, simply write the number 4 ). 1. For the HA, the delay of its sum bit is microseconds, and the delay of its carry bit is microseconds 2. For the FA, the delay of its sum bit is microseconds, and the delay of its carry bit is microseconds 3. The delay of the sum3 (most significant bit of the 4 bits 0..3 ) output of the RCA4 is microseconds