A behavioural description of an up/down counter is described in updown.v. The test bench verilog file is tb_updown.v. A simulation is run with: iverilog tb_updown.v updown.v && vvp a.out Replace the behavioural description in updown with adders, subtractors, multiplexors and d flip-flops modules. Test the modified code with: iverilog tb_updown.v updown.v && vvp a.out

updown.v:

module updown( count, up, down, reset, clk ); output reg [7:0] count; input up, down, reset, clk; // replace the behavioural description // with adders, subractors, multiplexors, and // d flip-flops always @(posedge clk) begin if ( reset ) count <= 0; else if ( up ) count <= count + 1; else if ( down ) count <= count - 1; end endmodule 

tb_updown.v:

`timescale 1ns / 1ns module main; reg up=0, down=0, reset=1, clk=0; wire [7:0] count; updown test( count, up, down, reset, clk ); always #1 clk = ~clk; initial begin $monitor("up=%b down=%b reset=%b count=%d", up, down, reset, count); $display("checking reset"); #4; $display("checking up count"); reset = 0; up = 1; #8; $display("checking down count"); up = 0; down = 1; #12; down = 0; $display("checking no counting"); #6; $display("checking reset"); reset = 1; #4; $finish; end endmodule