A chain of static CMOS gates is shown below. The gate represented with the rectangle is a complex gate implementing Y = [X2(X3+X4)]'. All of the gates are built with 125-nm wide NMOS and PMOS devices. Assume 2.5-fF load capacitance for each gate. How long is the latency of this chain from X to Y? X Logic-I- Logic-I- D X X3 Logic-I- Y=[X2(X3+X4)] Logic-0 X4 Logic-I-