A circuit receives a 4 bit binary number representing integers in the range 0 n 15 at its input. Its output is required to be '1' if the input represents a prime number (2, 3, 5, 7, 11 or 13) and '0' otherwise. Hint: If the number is ABCD, one can show using a Karnaugh map, that the logic function is: (A+B) CD+A.B.C+B.C.D. Implement this function in a 4 phase dynamic logic circuit using only NAND, NOR and inverter gates with no more than 3 inputs for any gate. The four input bits are valid only during phase 1 of a single clock cycle. Complements of these are not provided and should be generated using 4 phase dynamic inverters if required. Only a logic diagram is to be provided and not a transistor level circuit. Each logic gate should be labelled with a number written inside its symbol, representing its evaluation phase. The circuit should produce the output in as few clock phases as possible.