A circular queue is seen as an array that wraps around back to its first index after it surpasses its last index (aka its length). This circular queue (or Ring Buffer as its sometimes called) follows the FIFO convention (aka First In First Out) which means data is retrieved out of the buffer using this convention (think of it as people waiting in a line; the first ones in are the first few to leave the line). To keep track of this circular queue, we need 2 pointers: a Head and a Tail. The Head will keep track of the element that is the front-most in the line/queue while the tail will point to the next available location for new data to be placed into. These pointers will also help us establish the various states of the queue: empty, used, and full. We can say that when Head and Tail are equal to each other, then the queue is empty. We can also say that when (Tail + 1) is equal to head, then the queue is full. One tricky case here, is the nature of the circular queues boundary: being when it wraps back around itself. In a C code implementation, one could use modulo (or %) of the size of the buffer (i.e. 1 % 8 = 1, 2 % 8 = 2, 8 % 8 = 0, etc.) so that when one of the pointers reach the size of the buffer, the modulo of that pointer with the size of the buffer will set it back to 0. In the case with using Verilog, if one chooses the buffer size to be powers of 2, then one should not need the modulo operation because the register would overflow back to 0 (i.e. with a reg of 3-bits: 110 + 1 = 111 and 111 + 1 = 000). In our case, we need to design a circular queue with a size of 8 locations so we should not need to worry about doing modulo operations in our particular lab assignment. The data size at each location will be 8-bits for this lab.

Fill in the rest of the verilog template code where it says "finish writing code here".

thank you

Template Code:

module FIFO ( input [7:0]dataIn, input clk,enqueue,dequeue, output reg full,empty, output [7:0]dataOut ); // enqueue = "place" and dequeue = "remove" // Declare State Constants... localparam [1:0] EMPTY = 2'b00, USED = 2'b01, FULL = 2'b10; // Declare Circular Queue... reg [7:0]buffer[7:0]; // Declare Registers... reg [2:0]head,headNext,tail,tailNext; reg [1:0]state,stateNext; reg emptyNext,fullNext; initial begin head = 'd0; tail = 'd0; headNext = 'd0; tailNext = 'd0; state = 'd0; stateNext = 'd0; full = 0; fullNext = 0; empty = 1; emptyNext = 1; end // Current State Logic... always@(posedge clk) begin state <= stateNext; head <= headNext; tail <= tailNext; full <= fullNext; empty <= emptyNext; end // Next State Logic... always@* begin stateNext = state; headNext = head; tailNext = tail; emptyNext = empty; fullNext = full; case(stateNext) EMPTY: begin if(enqueue) begin // Finish writing code here... end else stateNext = EMPTY; end USED: begin if(enqueue) begin // Finish writing code here... end else if(dequeue) begin // Finish writing code here... end else stateNext = USED; end FULL: begin if(enqueue) stateNext = FULL; else if(dequeue) begin // Finish writing code here... end else stateNext = FULL; end endcase end assign dataOut = buffer[head]; endmodule