A CMOS logic gate that implements the function: F=(x*(y+z)+x*w)' in needed in a control network.

a) Design the logic circuit. An inverter with beta_n=beta_p is used as a sizing reference.

b) Find the device sizes in the gate if we choose to equalize the nFET and pFET resistances.

c) Suppose instead that we use transistors that are the same size as the inverter values. Identify the worst-case nFET and pFET paths that will slow down the response.