a$)$ Complete the timing diagram of the logic circuit whose VHDL description is shown below:

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity circ is

port $(a,b,c$ : in std$\_$logic;

f: out std$\_$logic$)$;

end circ;

architecture st of circ is

signal $x,y$ : std$\_$logic;

begin

$x$not$(ax$@$b)$;

$yx$ nand $c$;

$f$ y xor $(nota)$;

end st;