(a) Consider an embedded system based around an 8-bit CPU that supports 16-bit memory addresses and uses memory mapped I/O. The CPU has separate control outputs for Read Enable (RE) and Write Enable (WE). The system has three peripheral devices: a 16 KiB ROM, a 4 KiB RAM, and a 16- register I/O device. (i) Sketch a high level circuit showing the main connections between the CPU and the peripheral devices. (ii) Briefly describe the sequence of signals and events required to read a byte of data from the ROM into the CPU. (b) Consider again the system described in part (a). Derive the algebraic expression for the address decoder logic required to select the RAM device whenever any valid address within the range of the RAM device is specified. The 4 KiB RAM device is mapped to memory starting at address 0x8000