A CPU has the same register set and memory access as the Very Simple CPU, but a different instruction set. 1. Complete the ISA by specifying the four new instructions, their instruction codes, and their overall functions. You can choose any functions you wish, but you must include at least one instruction that gets an operand from memory and at least one instruction that does not. 2. Show the state diagram and RTL code for the CPU. 3. Design the register section, ALU, and control unit for the CPU. Include the hardware to generate all control signals. Feel free to start with the hardware for the Very Simple CPU and modify it for the new CPU. 4. Trace the fetch, decode, and execute cycles for each instruction to verify the CPU implements the ISA correctly. Your solution should follow the format of Table 6.4.

Instruction State Active Signals Operations Performed Next State ADD 4FETCH PCBUS, ARLOADARO FETCH FETCH3 FETCH2 READ, MEMBUS, DR-04H, PC-I DRLOAD, PCINC FETCH 3IDROADARLOAD IR.-00 AR. 04H |ADO ADD READ, MEMBUS, DR-27H ADD2 DRLOAD AD02 I DRBUS, ACLO AD I AC.-0 + 27H-27H I FETCH Instruction State Active Signals Operations Performed Next State ADD 4FETCH PCBUS, ARLOADARO FETCH FETCH3 FETCH2 READ, MEMBUS, DR-04H, PC-I DRLOAD, PCINC FETCH 3IDROADARLOAD IR.-00 AR. 04H |ADO ADD READ, MEMBUS, DR-27H ADD2 DRLOAD AD02 I DRBUS, ACLO AD I AC.-0 + 27H-27H I FETCH