a) Design a 3-bit binary synchronous down-counter using J-K flip-flops. b) Draw the circuit diagram, using flip-flops as blocks (do not draw the individual gates in each flip- flop). Show and label all inputs and outputs. Assume the J-K flip-flops are rising-edge-triggered. c) For an output cycle of 10 clock pulses, draw the 3 outputs QQ and Q, of the synchronous counter