A digital radio data receiver has a noisy input signal, but thesignal is correct the majority of the time. The signal issampled 3 times per bit and if there are more ones than zeros, wewant to treat it as a one input. Design a Mealy state machinethat is a *majority vote* detector that indicates when the majorityof the last three samples received are ones. When at least 2out of the last 3 inputs received are ones, it will output a1. See the example input and output example sequence yourdesign must generate here:

Clock: 0 1 2 3 4 5 6 7 8 9 A B C D E F

In:    0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0

Out:   x x 0 1 1 1 0 0 0 1 0 1 1 1 0 0

When the first three bits (001 above) are received, atclock time 2 the output is 0, but when the next bit isreceived (011 above) at clock time 3, the output is 1,because two of the three inputs are one (011above).

1) Implement the sequence detector Mealy state machine described inRoth.

2) Implement the sequence detector Mealy state machine.