$($a$)$ Draw the block diagram for a divider that divides an $8-$bit dividend by a $5-$bit divisor to give a $3-$bit quotient. The dividend register should be loaded when $St=1.$

$($b$)$ Draw an SM chart for the control circuit.

$($c$)$ Write a VHDL description of the divider based on your SM chart. Your VHDL should explicitly generate the control signals.