a) Draw the detailed architecture of a Full Adder Cell using gates AND, OR and EXOR (as shown on the first page of c2_pages.pdf from Course support). Write a Full_Adder module using Verilog language implement the functionality of the previously designed combinational circuit. b) Build, using the Verilog language, the architecture of a 4-bit RCA using instances of the Full_Adder module implemented in point a).

Az B3 A B2 A1 B1 Ao C4 C3 C2 Ci Full Adder Full Adder Full Adder Full Adder S3 S2 Si So