A) Explain hazards caused by branch instructions in pipeline design. B) Assume RISC pipeline has five stages IF, ID, EX, MEM, and WB. Consider the following program that computes 1 + 2 + ... + 99 + 100. Lw R1, #100//load 100 to R1. Lw R2, #0//load o to R2 Lw R3, #0//load 0 to R3 Loop: Add R2, R2, R3//increase R2 by the value in R3. Add R3, R3, #1//Increase R3 by 1 Sub R1, #1//Decrease R1 by 1 BNEZ R1, LOOP//go to Loop if R1 is not zero Point out the branch hazard, and show how to insert an instruction into the branch delay slot so that the pipeline stalls are reduced