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a) Find the addressing mode of the next assembly instructions. b) How many cycles has each instruction? | Clock Cycles MNEMONIC PUSH {R2,R3) Delay Loop:
- a) Find the addressing mode of the next assembly instructions.
- b) How many cycles has each instruction?
| Clock Cycles MNEMONIC PUSH {R2,R3) Delay Loop: LDR R2,M ADDRESS MODE register addressing media Address irea Tev in rective accessing Delay Loopl: SUB R2.(R1,1] CMP R2,[R1,#OxA6]! BNE Delay Loopl SUB R3, R2,#1 CMP R3,#0 BNE Delay_Loop POP R2,R3) MOV PC,LR med dessing medice Address Yitive Acklessing register addressing register addressing main: BL Init GPIO LDR RO.GPIO PORTF DATA R MOV R1,#00000000b STR R1,[RO),#0x9C relative addess Immediate addressing immediate addressing Posted desig Loop: LDR RI,[RO] AND RI,R3,#00010001b CMP R1,#000100006 BEQ GRED CMP R1,#000000016 BEOGBLUE CMP R1,#00000000b BEQ GGREEN B Loop register addressing mediche Addresing immediate addressing Celore addicessine immediate addressing relative addressing Immed are addressive tive addressing YeLove and sing Init GPIOF: PUSH RO,R1) LDR RO,SYSCTL RCGC2 R LDR RI,SYSCTL RCGC2 Data STR R1,[RO,LSR #9] LDR RO, GPIO PORTF LOCK R LDR RI,PORTF LOCK DATA STR R1,[RO] LDR RO, GPIO PORTF CRR MOV RI,#OxIF registry addressing M AX Addressing immediate addressing PC indesc address www.edite sdressing Winche dovessing reqisice lodic mediers adding wmediate addressing STD DIR01 immediate T ecliche Yegister indirect immediate Ammate immedia immedias POST in wedere Pre Indexed Yaster indirect immediate immacolate register indirect register LDR RO, GPIO PORTF_AFSEL_R MOV R1,#0x00 STR R1,[RO LDR RO, GPIO PORTF PCTL R MOV R1,#Ox00 STR R1,[RO,%00101101]! LDR RO, GPIO PORTF DIR R MOV R1,#OxOE STR R1,[RO],#SA3 LDR RO.GPIO PORTF PUR R MOV R1, R7,#0x111 STR R1,[RO] LDR RO, GPIO PORTF DEN R MOV R1,#0x1F STR R1,[RO] POP {RO,RI) Bx LR RED LED: PUSH (R1,R2 DITSHRI R2 MOV R1,#00000010b STR RI,[RO] MOV R3.5 PUSH {r5-r7,1r) BL Delay POP {r5-17.pc) MOV R1,#00000000b STR R1,[RO] POP (R1,R2} BLUE LED: PUSH R1,R2} MOV R1,#00000100b STR R1,[RO] MOV R3,#5 PUSH {r5-r7, Ir} BL Delay Tam edicte Yegister_direct immediate register Kelative Yegister mediate register Indirect register Kelster Mcdicure register immediate register rective | Clock Cycles MNEMONIC PUSH {R2,R3) Delay Loop: LDR R2,M ADDRESS MODE register addressing media Address irea Tev in rective accessing Delay Loopl: SUB R2.(R1,1] CMP R2,[R1,#OxA6]! BNE Delay Loopl SUB R3, R2,#1 CMP R3,#0 BNE Delay_Loop POP R2,R3) MOV PC,LR med dessing medice Address Yitive Acklessing register addressing register addressing main: BL Init GPIO LDR RO.GPIO PORTF DATA R MOV R1,#00000000b STR R1,[RO),#0x9C relative addess Immediate addressing immediate addressing Posted desig Loop: LDR RI,[RO] AND RI,R3,#00010001b CMP R1,#000100006 BEQ GRED CMP R1,#000000016 BEOGBLUE CMP R1,#00000000b BEQ GGREEN B Loop register addressing mediche Addresing immediate addressing Celore addicessine immediate addressing relative addressing Immed are addressive tive addressing YeLove and sing Init GPIOF: PUSH RO,R1) LDR RO,SYSCTL RCGC2 R LDR RI,SYSCTL RCGC2 Data STR R1,[RO,LSR #9] LDR RO, GPIO PORTF LOCK R LDR RI,PORTF LOCK DATA STR R1,[RO] LDR RO, GPIO PORTF CRR MOV RI,#OxIF registry addressing M AX Addressing immediate addressing PC indesc address www.edite sdressing Winche dovessing reqisice lodic mediers adding wmediate addressing STD DIR01 immediate T ecliche Yegister indirect immediate Ammate immedia immedias POST in wedere Pre Indexed Yaster indirect immediate immacolate register indirect register LDR RO, GPIO PORTF_AFSEL_R MOV R1,#0x00 STR R1,[RO LDR RO, GPIO PORTF PCTL R MOV R1,#Ox00 STR R1,[RO,%00101101]! LDR RO, GPIO PORTF DIR R MOV R1,#OxOE STR R1,[RO],#SA3 LDR RO.GPIO PORTF PUR R MOV R1, R7,#0x111 STR R1,[RO] LDR RO, GPIO PORTF DEN R MOV R1,#0x1F STR R1,[RO] POP {RO,RI) Bx LR RED LED: PUSH (R1,R2 DITSHRI R2 MOV R1,#00000010b STR RI,[RO] MOV R3.5 PUSH {r5-r7,1r) BL Delay POP {r5-17.pc) MOV R1,#00000000b STR R1,[RO] POP (R1,R2} BLUE LED: PUSH R1,R2} MOV R1,#00000100b STR R1,[RO] MOV R3,#5 PUSH {r5-r7, Ir} BL Delay Tam edicte Yegister_direct immediate register Kelative Yegister mediate register Indirect register Kelster Mcdicure register immediate register rective
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