a) Find the # of system clocks required for the value which is 16 times the baud rate. Baud rate is computed by multiplying the two numbers present in your Roll number (e.g. SP20-BEL-73). b) Write a Verilog code of a module that counts number of system clock cycles. Module generates a pulse of width equal to one system clock cycle, when it reaches to the value computed in part a. This module works repeatedly till the hardware switch off or reset. No. 2: (5,10) a) What is the suitable On.m format for the two numbers given in your Roll number (e.g. SP20-BEL-73)? b) Write Verilog code of fixed point Qn.m multiplier, for the On.m format computed in part a. (10, 10) D.No.3: a) Write Verilog code for the given ASMD chart b) Write Verilog test bench for the ASMD design in part a. SO 11.-8 s1 11.11+12 FIFTE s2 r111