(a) For instruction accesses, we only need to consider the L1 instruction cache. The hit time is 3 cycles and the miss rate is 4%. Thus, the average memory access time for instruction accesses is: Average memory access time = hit time + miss rate miss penalty = 3 cycles + 0.04 (1 / 0.96) 12 cycles = 3.5 cycles

why miss penalty is (1/0.96) * 12???