$($a$)$ Given the data path of a CPU as shown below:

CPU$-$Bus

Figure $1$: A simplified CPU

In the data path shown, the S$1,$ S$2$ and D fields in the instruction represent the two

source and one destination operands, and are directly connected to the address

port of the register file. Register S$1$ will be read into RFOUT$1,$ while register S$2$

will be read into RFOUT$2.$ RFIN will be written into register D$.$ Registers A and B

are the input registers and C the output register of the ALU. There is a single

CPU bus in the data path.

We would like to add a function call $($CALL$)$ and return $($RET$)$ instruction to the

processor.

$($i$)$ Describe the required modification to the registers and data path of the

CPU in order to implement the added instructions. $[3].$

$($ii$)$ Write down the data transfer and transformation sequences for the function

call and return instructions, including instruction fetch. $[8]$

The following is the format of the added instructions: The two$-$word instruction

CALL OFF$($R$1)$ where OFF$($R$1)$ is the displacement addressing mode to specify

the address containing the target address of the function call, OFF stored in

the second word of the instruction.

The one$-$word instruction RET:

$($b$)$ The CPU XT$-360$ uses an one$-$instruction format. For example, the instruction

ADD has the format ADD R$1,$ where R$1$ is the explicit register operand.

$($i$)$ How many operands do the ADD intruction have, and where are the other

operands not specified? $[2]$

$($ii$)$ What kind$($s$)$ of pipeline hazard exist in the following instruction sequence?

Explain. $[3]$

ADD R$1$

SUB R$3$

$($iii$)$ Suggest a way to re$-$design the instruction format so that there will be less

pipeline hazard described in $($ii$).[3]$