a) I,III

b) I, II, III

c) I, III, IV

d) II, IV

Which of the following is true for the two verilog codes given? 1. Behavioral design level is used. II. Output(y) is equal to logic 1 and the text " y=log ic 0 " appears in the simulation. III. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output