a. In HW 3 you designed a prime number detector. One of the sum-of products logic equations that implements is f(a, b, c, d) -a b'cb'cd + bc'd+ a'cd. Write a structural model for the circuit using Verilog primitive gates. Use the following module declaration and port declaration to define your circuit: module prime detector (a, b, c, d, f); input a, b, c, d; output f: // INSERT THE CODE FOR YOUR PRIME NUMBER DETECTOR HERE endmodule Add wire declarations as needed by the structure of the circuit you are describing in Verilog. You may use AND gates, OR gates, and inverters. Your AND gates and OR gates may have any number of inputs. b. Compile and simulate the circuit in Quartus. Submit the waveform showing all inputs and outputs. a. In HW 3 you designed a prime number detector. One of the sum-of products logic equations that implements is f(a, b, c, d) -a b'cb'cd + bc'd+ a'cd. Write a structural model for the circuit using Verilog primitive gates. Use the following module declaration and port declaration to define your circuit: module prime detector (a, b, c, d, f); input a, b, c, d; output f: // INSERT THE CODE FOR YOUR PRIME NUMBER DETECTOR HERE endmodule Add wire declarations as needed by the structure of the circuit you are describing in Verilog. You may use AND gates, OR gates, and inverters. Your AND gates and OR gates may have any number of inputs. b. Compile and simulate the circuit in Quartus. Submit the waveform showing all inputs and outputs