(a) Insert Simulink system block diagram of your design of the Convolution Encoder. Explain how your design works. (make sure your figures or diagrams are clear and readable) (b) Show and compare your designs output results with that from standard Simulink block-set. Justify how your design was met the requirement. (make sure your figures or diagrams are clear and readable) (c) Implement the Convolution Encoder using System Generator for DSP tool. Insert your design block diagram. (make sure your figures or diagrams are clear and readable) (d) Verify your System Generator for DSP design by using your Simulink model in (a). Justify your design met the requirement. (make sure your figures or diagrams are clear and readable) (e) Synthesis your design using Xilinx Vivado tool and comment on the resources (slices and registers) usage and maximum operation speed on a FPGA device as your choice. (make sure your figures or diagrams are clear and readable) (f) Assume that a design failed the speed requirement, discuss the potential techniques that can be used to improve the design to meet the speed requirement.