A JK flip flop is currently in Set State. At the positive edge of the clock pulse, J and K input changes to J=0, K=0. At the next positive edge of the clock pulse J=K=1. What will be the state of the flipflop at this stage? O Toggle state with Q=0,Q'=1 O Toggle state with Q=1,Q'=0 Latch state with Q=0,Q'=1 O Latch state with Q=1,Q'=0