A k-way set associative cache consists of 128 lines divided into four-line sets. M 64K blocks of 16 bytes each. i. What is k? (1 point) ii. What is the format of main memory address? (4 points) ii. What is the size of the cache in bytes? (2 points) 16 For the same size cache and block size as part (a), what would be the format of main memory address if direct cache is to be designed? b. 16 e. Design a 32-bit memory of total capacity 32768 bits using SRAM chips of size 64x4. Give the array configuration of the chips on the memory board showing all input and output signals for assigning this to the lowest address. The design should allow byte, word and double word accesses