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A MIPS assembly code is shown below. The assembly code is executed using a 5 - stage MIPS processor and we can actually decide the
A MIPS assembly code is shown below. The assembly code is executed using a stage MIPS processor and we can actually decide the branch a little earlier, in ID instead of EX Answer the following questions: Loop: sub $ $ $ addi $ $ sw $$ addi $ $ sll $ $ $ add $ $ $ addi $ $ sll $ $ add $ $ $ lw $$ sub $ $ $ sw $$ beq $ $ Loop addi $ $a How many clock cycles are needed to execute the code above? Assume there is no forwarding, no branch prediction.b How many clock cycles are needed to execute the code above? Assume there is forwarding, no branch prediction.c Reorder the above code to reduce the stalls get the smallest number of stalls without changing the functionality. Assume there is forwarding and no branch prediction. How many clock cycles are needed to execute the code above?
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