A NAND gate has been added as a feedback path for the shift register shown below. The outputs of the circuit are q[3]-q[o]. The initial state of the shift register is provided in the timing diagram below. Complete the timing diagram. 3. q13] q[2) q[O] D91) clk clr clk clr D a clk clr clk clr clk clr 20 .40 60.80 . Signal name clk a clr 913) [2] q11 - 910