A NAND gate has been added as a feedback path for the shift register shown below. The outputs of the circuit are q[3] q[0]. The initial state of the shift register is provided in the timing diagram below. Complete the timing diagram. 3. q[3] q12] q[0] clk clr clk clr clk clr clk clr clk clr Signal name - clk o clr E q[3:0] o q13] o 12] o q[0]