A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI of 4. An upgrade to the processor introduces a four-stage pipeline with each stage executing in one clock cycle. However, due to the need for extra buffers between the stages, the clock rate of the new processor has to be reduced to 2 GHz. a) What are the MIPS of the original processor and of the pipelined processor? b) What is the speedup of the pipelined processor over the original processor? c) A benchmark program runs on the original processor in 120 ms. How long will it take to run on the pipelined processor? Question 2. Consider the following table 3 for latencies and the code given in question 1 (consider populate table 1 and table 2 for clock cycles). IF 150 ps ID 100 ps EX 200 ps Table 3. MEM 250 ps WB 120 a. Calculate the ratio of the CPU Time (non-pipelining processor) to the CPU Time (pipelined processor WITHOUT forwarding). (5 points) b. Calculate the ratio of the CPU Time (non-pipelining processor) to the CPU Time (pipelined processor WITH forwarding). (10 points) c. Calculate the ratio of the CPU Time (pipelined processor WITHOUT forwarding) to the CPU Time (pipelined processor WITH forwarding). (10 points) 2